It is known to provide data processing systems such as integrated circuits having processing logic that is sub-divided into several clock domains which require gated or different frequency clocks to be generated and distributed with controlled “clock skew” between them to allow signals to pass between the different clock domains without timing violations. Clock skew is defined herein to be a situation where corresponding rising and/or falling edges of two different clock signals are non-coincident.
It is known in systems such as Field Programmable Gate Arrays (FPGA) to provide a number of low skew global clock buffers with similar distribution insertion delays. However, it is difficult, for example, to generate clocks which are integer divisions of each other frequencies while maintaining low skew between the output clocks. In particular, there is no “clock re-synthesis” or clock balancing included in the known FPGA tools to support this. It is also known to use static timing analysis tools to perform static timing checks that can be used to analyse particular portions of the circuit. However, such static timing analysis tools are not capable of analysing clock paths that are external to an FPGA such as clock paths that are involved in generation and distribution of the clocks via board-level components before those clocks are passed into the FPGA.
Although it is possible to explicitly place circuit elements such as flip-flops and clock buffers to arrange that there is reduced clock skew between generated functional clocks, such fine-tuning of the circuit design is inherently error prone since differing magnitudes of delay could be inadvertently placed in different clock paths resulting in non-negligible clock skew. Furthermore, such a methodology is not easily transferable to different sizes and structures of programmable logic devices.
It is known in systems such as Phase Locked Loop (PLL) clock generators to generate a further clock in dependence upon a reference clock and to modify the relative timings of the clock edges of those two clocks to achieve the desired clock signal profiles. Since the PLL actually generates the clock signals, the signal profiles of those clock signals can be readily controlled by the PLL to reduce any clock skew. However, in data processing devices where the clock signals are externally generated and received as inputs, it is much more difficult to control any clock skew.
Thus there is a requirement for a more efficient mechanism of controlling clock skew between at least two input clock signals that provides reliable clock skew detection and enables the clock skew between different input clock signals to be efficiently controlled.